A basic diagram for a known type of multistage operational amplifier is illustrated in FIG. 1. The amplifier includes an input transconductor stage marked as reference 10. The transconductor stage 10 includes a differential input with two input terminals 12+ and 12-, and a current output 14. The input terminals 12+ and 12- respectively correspond to a non-inverting input and an inverting input. Output 14 is connected to a system of gain stages including, in order, a first intermediate stage 20, a second intermediate stage 30 and an output stage 50. The stages are connected in parallel between power supply terminals 1 and 2.
The first and second intermediate stages and the output stage respectively include first, second and third bipolar transistors 22, 32 and 52 in a common-emitter configuration. The transistors 22, 32 and 52 are biased by respective current sources 24, 34 and 54. The base and collector of each transistor forms the respective input and output terminals of the corresponding stage.
The base of the first bipolar transistor 22 is connected to the current output 14 from the input stage 10, and its collector is connected to the base of the second transistor 32. Furthermore, the collector of the second transistor 32 is connected to the base of the third transistor 52 of the output stage. The collector of the third transistor 52 forms an amplifier output terminal 56. The output terminal is more precisely identified as reference 56. The output stage 50 is connected to an external load L shown as a discontinuous line. This load, which does not form part of the amplifier, is considered as having an impedance with a capacitive component equal to C1.
FIG. 1 also shows a number of capacitors. A second Miller capacitor 60 with value CM is connected between the input of the first stage 20, i.e., the base of the first transistor 22, and the amplifier output terminal 56. A first Miller capacitor 62 with value CM.sub.2 is connected between the base and the collector of the first transistor 22, i.e., between the input and the output of the first intermediate stage 20. A third Miller capacitor 63 with value CM.sub.3 is connected between the base and the collector of the third transistor 52, i.e., between the input and the output of the output stage 50.
Capacitors 60, 62 and 63 are frequency compensation capacitors that stabilize the amplifier in a closed loop. These capacitors are usually referred to as "Miller capacitors". Other capacitors of the same type may be provided. In general, frequency compensation capacitors are connected between the input of a given stage and the output of the stage, or the output of a next stage, in the sequence of gain stages.
The terms "next" and "previous" used herein refer to a defined direction in the sequence of stages starting from the input stage and working towards the output stage. This is the direction in which a signal passes through the amplifier. The Miller capacitors and external capacitors connected to the amplifier govern its own frequency behavior and the frequency behavior of each of its stages. This behavior is characterized by poles. The poles correspond to the frequencies at which modifications to the gain slope are observed in a frequency response diagram or a Bode diagram. The Bode diagram expresses the amplifier gain as a function of the frequency of a signal passing through the amplifier.
As shown in the example in FIG. 1, a first pole p.sub.1 can be defined corresponding to the output stage 50 and generated by the capacitive part of the external load L connected to the amplifier output. The expression of the first pole p.sub.1, for which the dimension is a pulse, is such that: ##EQU1##
In this expression, C1 is the capacitive value of the load L and gm.sub.3 is the transconductance of the third transistor 52, i.e., the output stage.
The first pole corresponds to a frequency f.sub.1 such that: ##EQU2##
In the same way, a second pole corresponding to the second intermediate stage 30 can be defined. This pole is an intermediate pole and corresponds to a pulse P.sub.2 for which the expression is more complex. The result is: ##EQU3##
CM, CM.sub.2, CM.sub.3 are the respective values of the first, second and third capacitors, and gm.sub.2 is the transconductance of the second transistor 32. The second pole has a frequency: ##EQU4##
Finally, a frequency called the unit gain frequency associated with the first capacitor 60, with value equal to CM, is provided to stabilize the amplifier in a closed loop. The expression of the unit gain frequency of the amplifier, denoted f.sub.gu, is: ##EQU5##
In this expression gm denotes the transconductance of the input stage 10.
The values CM, CM.sub.2 and CM.sub.3 must be chosen to satisfy the following stability equation in order to stabilize the amplifier, in other words, to avoid a parasitic oscillation phenomena: EQU f.sub.gu.ltoreq.k.sub.2 f.sub.2.ltoreq.k.sub.1 f.sub.1
The variables k.sub.1 and k.sub.2 are multiplication factors such that k.sub.2 &gt;1, k.sub.1 &gt;1.
The equation shown above, called the first stability equation, represents the fact that the frequencies of the poles introduced in the successive stages from the input to the output of the amplifier must be increasing and distinct. This rule, applicable to the example in FIG. 1, remains true for an amplifier with a different number of gain stages. The values of the multiplication factors k and k', usually equal to 2, must be chosen to be greater than 1 to insure that the poles are not coincident. A large value for these factors results in the amplifier having good stability.
As described above, the choice of Miller capacitors is dictated by the stability equation. The capacitors are chosen particularly to satisfy the stability equation when the transistors in the gain stages carry an amplifier rest current. This rest current is the current that conducts through the transistors in the gain stages when there is no signal applied to the amplifier input.
For a given stage with one or more bipolar transistors, the value of the transconductance depends on the current in the collector of the transistor(s). More precisely, for each intermediate stage: ##EQU6##
In this expression, gm.sub.i and I.sub.i respectively denote the transconductance and the collector current of the transistor in the stage considered. The term V.sub.t is a thermal voltage defined by: ##EQU7##
where T is the temperature, k is the Boltzmann constant and q is the electron charge. Thus, for a second intermediate stage in which the collector current is denoted IC.sub.2, we have: ##EQU8##
When a signal is applied to the amplifier input, collector currents different from rest currents pass through the transistor collectors. Thus, the values of pole frequencies that depend on transconductances are modified and tend to increase. This phenomenon is referred to as frequency excursion of the poles. The frequency excursion of the poles depends essentially on the gains of the transistors used and external usage conditions of the amplifier that define collector currents in the stages.
The behavior of the amplifier is also characterized by one or several zeros that correspond to inflections in the amplifier phase curve. The phase curve is equal to the phase difference between the amplifier output and input, expressed as a function of the frequency. Each stage of the amplifier including a capacitance that may or may not be parasitic, may cause a zero in the phase curve. This subject is described in more detail in "Analysis and Design of Analog Integrated Circuits", by Paul R. Gray and Robert G. Meyer, Third Edition, page 621, .sctn.9.4/3, eq. 9/27a, FIGS. 9-23, John Wiley & Sons, Inc.
In the example in FIG. 1, the first Miller capacitor 62 in the first intermediate stage introduces a zero denoted z.sub.0 for this stage, the expression of which is: ##EQU9##
The variable gm.sub.1 is the transconductance of the transistor in the first stage.
The zero corresponds to a frequency f.sub.0 such that: ##EQU10##
The stability of the amplifier imposes a sufficient separation of the frequency f.sub.0 and frequencies corresponding to the amplifier poles. A second stability equation can be defined with reference to the first stability equation given above, expressed as f.sub.0 &gt;f.sub.1 or, in other words, z.sub.0 &gt;p.sub.1.
As mentioned above, the collector currents and the transconductances of the stages are known at rest, i.e., when no signal is applied to the amplifier. Therefore, the values of the Miller capacitors can be chosen such that the stability equations are satisfied. When the amplifier outputs high currents, the currents in the intermediate stages also vary. Since the conductances of the stages are proportional to the collector current in the corresponding bipolar transistors, the values of the poles and zeros change.
However, changes to poles and zeros are not uniform and stability equations may no longer be satisfied for high currents. For example, with reference to FIG. 1, the output current at terminal 56 increases when the collector current in transistor 52 in the output stage 50 increases. The increase in this current causes an increase in the transconductance gm.sub.3 and, therefore, the frequency f.sub.1, the expression of which was given previously.
The transistors in the output stage 50 and the second intermediate stage 30 are of a type with opposite conductivities, PNP and NPN respectively. The base current in transistor 52 in the output stage is thus added to the current, denoted I.sub.2, that conducts through transistor 32 in the second intermediate stage 30. Therefore, an increase in the amplifier output current causes an increase in the current I.sub.2 in transistor 52. As described above, this causes a frequency excursion of the pole p.sub.1 of the output stage, for which the frequency f.sub.1 increases.
The transistors in the first and second intermediate stages are both of the NPN type. The base current of transistor 32 of the second intermediate stage 30 is subtracted from the collector current of transistor 22 in the first intermediate stage. Thus, when the amplifier output current increases, the collector current in transistor 22 in the first intermediate stage reduces.
A reduction of this current also reduces the transconductance gm.sub.1 and, therefore, the frequency f.sub.0 of the zero. Thus, if f.sub.0 decreases too much and f.sub.1 increases too much, the second stability equation may no longer be valid. The example given above with reference to FIG. 1 shows the disturbances that can occur following a frequency excursion of the poles and the zeros of an amplifier.
At high frequency, additional zeros or poles may also occur due to the increasing influence of parasitic capacitances that are negligible at low frequency. These zeros or poles also produce instabilities and oscillations of the amplifier when their frequencies intersect or do not satisfy stability equations.
One approach to prevent these oscillations includes limiting the maximum amplifier output current such that the frequency excursion of the poles and zeros remains moderate compared with the values defined with a rest current. However, this approach is not satisfactory, particularly for amplifiers that may be powered at low voltage. The output current limitation would reduce the power that could be controlled by the amplifier.